As integrated circuit technology continues to scale down to smaller geometries, the supply voltages are also being lowered to reduce power consumption. Although lowering the supply voltages helps to reduce power consumption, lowering the supply voltages may have the unintended consequence of increasing leakage. Memory circuits such as SRAM and SRAM-based components such as cache memories are typically more susceptible to erroneous operation resulting from leakage than other logic circuits. Because of this, as the supply voltages are lowered for integrated circuit devices that include SRAM-based components, for example, a microprocessor with cache memories, the SRAM-based components typically fail at a higher voltage level than the rest of the device. As such, the minimum voltage required to operate the SRAM-based components reliably tends to be the limiting factor on how low the supply voltage can be lowered. This effect is also referred to as the “Vccmin effect.”
Across different manufacturing process variations, a certain percentage of integrated circuit devices are expected to fail due to defects and/or device timing variations attributed to the manufacturing process. To ensure that defective devices are not sold or used in the field, reliability testing is typically performed at the manufacturing stage to determine if a particular device can operate reliably over a target range of operating conditions. If the particular device fails the reliability testing, the entire device is discarded. As the supply voltages are being lowered to reduce power consumption, in addition to the defective devices resulting from manufacturing process variation, an additional percentage of devices are expected to fail reliability testing due to the Vccmin effect described above. Hence, the lowering of supply voltages tends to have an adverse impact on the overall yield of the integrated circuit device. One way of mitigating this adverse impact for SRAM-based components is to implement error correction mechanisms such as Error Correcting Codes (ECC). However, implementing ECC comes at the cost of additional memory to store the ECC bits, a reduction in performance due to the additional time needed to perform the error correction operations, and an increase in power consumption associated with performing the error correction operations. Furthermore, the number of erroneous bits that can be corrected by ECC is limited.